ZYNQ学习笔记(二)

ZYNQ学习笔记(二)

疑问

  1. 所有AXI4总线上主设备和从设备之间的位宽要一样吗?可以不一样
  2. 怎么写flag?

知识点

  1. 状态机,从细节出发(一段式、两段式、三段式,moore型、mealy型)

  2. 黄标为握手后第一个数据(注意上升沿)

  3. 前仿真功能正常,但是后仿真显示该端口接地

    原因是data_num在两个always块被赋值

  4. PS-PL接口

    PL Interface Comparison Summary

    ug1037-vivado-axi-reference-guide

    ug1085-zynq-ultrascale-trm

    Exploring the PS-PL AXI interfaces on Zynq UltraScale+ MPSoC

  5. 固化https://blog.csdn.net/qq_39507748/article/details/116072620

IP核

JTAG2AXI

matlab安装HDL Verifier Support Package for Xilinx FPGA Boards

  1. https://ww2.mathworks.cn/help/releases/R2020a/hdlcoder/examples/using-jtag-as-axi-master-to-control-hdl-ip-core.html

  2. Set Up AXI Manager

    To access the board from MATLAB, create an aximanager object and use the readmemory and writememory methods to read and write memory-mapped locations on the board.

    Access Memory on FPGA Board from MATLAB

    Before you can use this example, you must have a design running on an FPGA board connected to the MATLAB host machine. The FPGA design must include an AXI manager IP that is customized for your FPGA vendor. The support package installation includes this IP. To include the IP in your project, see the Access FPGA Memory Using JTAG-Based AXI Manager example.

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    h = aximanager('Xilinx','JTAGCableType','FTDI');
  3. Access FPGA Memory Using JTAG-Based AXI Manager

Axi Bram_contorller

存储深度在Address Editor 中修改。其中最小为4K,最大为32M。

  1. Block Memory: Use BRAM Controller and Standalone mode at the same time?
  2. 注意AXI4 Interface Block Memory Addressing,地址有偏移 ( PG058 BRAM 用户指南第24)
  3. 关于Bram_contorller开启bram的功能【IP分析】BRAM的实用功能

问题记录

axi_bram_ctrl中bram位宽选择256位时

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write 0xC000_0000 0x12345678_ABCDEF01_23456789 3
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x12345678_ABCDEF01_23456789
read 0xC000_0000 3
INFO: [Labtoolstcl 44-481] READ DATA is: 12345678ABCDEF0123456789
0x12345678ABCDEF0123456789

选择32位时,发现写进去的和读出来的不一致

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write 0xC000_0000 0x12345678_ABCDEF01_23456789 3
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x12345678_ABCDEF01_23456789
read 0xC000_0000 3
INFO: [Labtoolstcl 44-481] READ DATA is: 123456781234567812345678
0x123456781234567812345678
read 0xC000_0000 1
INFO: [Labtoolstcl 44-481] READ DATA is: 12345678
0x12345678
read 0xC000_0000 2
INFO: [Labtoolstcl 44-481] READ DATA is: 1234567812345678
0x1234567812345678
read 0xC000_0000 8
0x1234567812345678123456781234567812345678123456781234567812345678

###
write 0xC000_0000 0x87654321
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x87654321
read 0xC000_0000 2
INFO: [Labtoolstcl 44-481] READ DATA is: 8765432187654321
0x8765432187654321
write 0xC000_0004 0x12345678
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x12345678
read 0xC000_0000 2
INFO: [Labtoolstcl 44-481] READ DATA is: 1234567812345678
0x1234567812345678

问题关键点在于数据位宽上

可以发现,一开始axi_bram_ctrl选择256位宽后,bd里面bram显示的数据位宽是256,综合后RTL网表里显示的也是256,但当axi_bram_ctrl选择32位宽后,bd和综合后的网表显示的位宽仍然保留256的位宽,导致出现问题。

解决方式:删掉bram这个ip,重新加入。。。

AXI

  1. ZYNQ基础----通过AXI4接口从内存中读出数据
  2. AXI总线总结

AXI_VIP

  1. FPGA从入门到精通(番外篇1)-AXI VIP的使用

UART2AXI

  1. core_dbg_bridge
  2. Verilog-UART

串口

  1. ADC测试杂谈二:matlab操作串口向FPGA发信

RF Data Converter

文章

  1. 利用 RF Data Converter 保持同步
  2. RFSoC应用指南

阈值监测

  1. Sticky Over Mode 超过即置位,XRFdc_ThresholdStickyClear复位

  2. Sticky Under Mode 低于阈值一定周期后置位,XRFdc_SetQMCSettings 复位。低于阈值->信号小->改变QMC增益->信号增强,复位,重新检测电平

    1. Hysteresis Mode 超过即置位,低于下限阈值一段周期后自动复位。适用于AGC应用。

DAC

Distribute clock

单独使用一个DACBANK的dac时需要关闭时钟路由,否则会导致时钟输入不进去,DAC无法启动

Cordic

  1. CORDIC算法原理详解

DDS Compiler

  1. 浅入浅出Vivado IP之DDS Compiler

  2. Vivado DDS IP配置与仿真(1)正弦、余弦信号发生器

  3. phase dithering and taylor series 区别 PG141 P41

  4. SFDR 与位宽,补偿方法的关系 PG141 P42

BRAM

  1. Vivado 下 IP核之双端口 RAM 读写

  2. ena和wea不同同时拉高,先拉高ena,后仿真看出

  3. How to make Vivado infer a Master xilinx.com:interface:bram_rtl:1.0 interface on a RTL/Verilog Module?

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    (* X_INTERFACE_MODE = "Master" *)
  4. 【整合】FPGA调用RAM资源

URam

  1. 在前仿真中,uram读取延迟是1,但是后仿真正常(Vivado 2022.1)
    read latency of uRAM doesn’t change in simulation when you change optional output registers, why?

XPM_FIFO_ASYNC

Zynq-7000 Verification IP

How to use the Zynq-7000 Verification IP to Verify and Debug Using Simulation

Vivado

  1. IP核传播参数 UG994 P148

  2. FSM coding - 1 vs 2 vs 3 process style - which one is preferred

  3. 状态机详解(一段式、二段式、三段式)

  4. FPGA三段式状态机的思维陷阱

  5. Vivado strategies:
    针对性能:

        Perfornance_Explore
    
        Perfornance_ExplorePostRouteFhsopt
    
        Perfornance_WLBlockPlacement
    
        Perfornance_WLBlockPlacementFanoutopt
    
        Perfornance_NetDelay_high
    
        Perfornance_NetDelay_low
    
        Perfornance_Retiming
    
        Perfornance_ExtraTimingOpt
    
        Perfornance_Refineplacement
    
        Perfornance_SpreadSLLs
    
        Perfornance_BalanceSLLs
    

    针对布线拥塞:

        Congestion_ SpreadLogic_high
    
        Congestion_ SpreadLogic_medium
    
        Congestion_ SpreadLogic_low
    
        Congestion_ SpreadLogic_Explore
    
        以下三个针对SSI芯片: 
    
        Congestion_ SSI_SpreadLogic_high
    
        Congestion_ SSI_SpreadLogic_low
    
        Congestion_ SSI_SpreadLogic_Explore
    

    针对资源:

        Area_Explore
    
        Area_ExploreSequential
    
        Area_ExploreWithRemap
    

    针对功耗:

        Power_DefaultOpt
    
        Power_ExploreArea
    

    针对运行时间:

        Flow_RunPhysOpt
    
        Flow_RunPos tRoutePhysOpt
    
        Flow_Runtimcoptinized
    
  6. Intelligent Design Runs

HLS

  1. pp4fpgas-cnFPGA并行编程

PetaLinux

  1. mmap dma AXI Direct Memory Access

  2. 手把手教你在Windows下用WSL运行Vitis/Vivado/Petalinux

    在适用于 Linux 的 Windows 子系统上运行 Linux GUI 应用

Verilog

  1. 信号延迟

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    module data_delay #
    (
    parameter M = 8, // 设置数据宽度
    parameter N = 10 // 设置延迟时钟周期
    )
    (
    input clk,

    input [M-1:00] data_in,
    output [M-1:00] data_out
    );

    reg [M*N-1:00] data_r;
    always @ (posedge clk)
    begin

    data_r <= {data_r[M*(N-1)-1:0],data_in};
    end

    assign data_out = data_r[M*N-1:M*N-M];

    endmodule

方案

TDC

延迟线

  1. https://blog.csdn.net/qq_41305217/article/details/134232959
  2. “秒表”的设计-Time-to-Digital Converter-TDC浅析原理与公式化

多相位时钟

ADI

  1. analogdevicesinc.github.io/pyadi-iio
  2. antsdr-pynq
  3. ADI vs MathWorks Support libiio
  4. HighSpeedConverterToolbox
  5. python bonding for libiio

Others

  1. RFSoC_OPFB
  2. Microsoft’s VS Code for C/C++/Python Development on Xilinx Platforms
  3. Ethernet AXI Manager

ZYNQ学习笔记(二)

https://www.shjdgwj.cn/307bdbd04705/

作者

GWJ

发布于

2023-09-06

更新于

2024-01-29

许可协议

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